| Server IP : 13.213.54.232 / Your IP : 216.73.216.72 Web Server : Apache/2.4.52 (Ubuntu) System : Linux ip-172-31-17-110 6.8.0-1029-aws #31~22.04.1-Ubuntu SMP Thu Apr 24 21:16:18 UTC 2025 x86_64 User : www-data ( 33) PHP Version : 7.1.33-67+ubuntu22.04.1+deb.sury.org+1 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals, MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /lib/modules/6.8.0-1029-aws/build/arch/x86/include/asm/ |
Upload File : |
/* SPDX-License-Identifier: GPL-2.0-only */ /* * imr.h: Isolated Memory Region API * * Copyright(c) 2013 Intel Corporation. * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie> */ #ifndef _IMR_H #define _IMR_H #include <linux/types.h> /* * IMR agent access mask bits * See section 12.7.4.7 from quark-x1000-datasheet.pdf for register * definitions. */ #define IMR_ESRAM_FLUSH BIT(31) #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */ #define IMR_RMU BIT(29) #define IMR_VC1_SAI_ID3 BIT(15) #define IMR_VC1_SAI_ID2 BIT(14) #define IMR_VC1_SAI_ID1 BIT(13) #define IMR_VC1_SAI_ID0 BIT(12) #define IMR_VC0_SAI_ID3 BIT(11) #define IMR_VC0_SAI_ID2 BIT(10) #define IMR_VC0_SAI_ID1 BIT(9) #define IMR_VC0_SAI_ID0 BIT(8) #define IMR_CPU_0 BIT(1) /* SMM mode */ #define IMR_CPU BIT(0) /* Non SMM mode */ #define IMR_ACCESS_NONE 0 /* * Read/Write access-all bits here include some reserved bits * These are the values firmware uses and are accepted by hardware. * The kernel defines read/write access-all in the same way as firmware * in order to have a consistent and crisp definition across firmware, * bootloader and kernel. */ #define IMR_READ_ACCESS_ALL 0xBFFFFFFF #define IMR_WRITE_ACCESS_ALL 0xFFFFFFFF /* Number of IMRs provided by Quark X1000 SoC */ #define QUARK_X1000_IMR_MAX 0x08 #define QUARK_X1000_IMR_REGBASE 0x40 /* IMR alignment bits - only bits 31:10 are checked for IMR validity */ #define IMR_ALIGN 0x400 #define IMR_MASK (IMR_ALIGN - 1) int imr_add_range(phys_addr_t base, size_t size, unsigned int rmask, unsigned int wmask); int imr_remove_range(phys_addr_t base, size_t size); #endif /* _IMR_H */