| Server IP : 13.213.54.232 / Your IP : 216.73.216.166 Web Server : Apache/2.4.52 (Ubuntu) System : Linux ip-172-31-17-110 6.8.0-1029-aws #31~22.04.1-Ubuntu SMP Thu Apr 24 21:16:18 UTC 2025 x86_64 User : www-data ( 33) PHP Version : 7.1.33-67+ubuntu22.04.1+deb.sury.org+1 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals, MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /lib/modules/6.8.0-1029-aws/build/arch/m68k/include/asm/ |
Upload File : |
/* SPDX-License-Identifier: GPL-2.0 */ /* * Q40 master Chip Control * RTC stuff merged for compactness. */ #ifndef _Q40_MASTER_H #define _Q40_MASTER_H #include <asm/raw_io.h> #include <asm/kmap.h> #define q40_master_addr 0xff000000 #define IIRQ_REG 0x0 /* internal IRQ reg */ #define EIRQ_REG 0x4 /* external ... */ #define KEYCODE_REG 0x1c /* value of received scancode */ #define DISPLAY_CONTROL_REG 0x18 #define FRAME_CLEAR_REG 0x24 #define LED_REG 0x30 #define Q40_LED_ON() master_outb(1,LED_REG) #define Q40_LED_OFF() master_outb(0,LED_REG) #define INTERRUPT_REG IIRQ_REG /* "native" ints */ #define KEY_IRQ_ENABLE_REG 0x08 /**/ #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ #define SAMPLE_RATE_REG 0x2c #define SAMPLE_CLEAR_REG 0x28 #define SAMPLE_LOW 0x00 #define SAMPLE_HIGH 0x01 #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ #if 0 #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ #endif #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) /* RTC defines */ #define Q40_RTC_BASE (0xff021ffc) #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) /* some control bits */ #define Q40_RTC_READ 64 /* prepare for reading */ #define Q40_RTC_WRITE 128 /* define some Q40 specific ints */ #include <asm/q40ints.h> /* misc defs */ #define DAC_LEFT ((unsigned char *)0xff008000) #define DAC_RIGHT ((unsigned char *)0xff008004) #endif /* _Q40_MASTER_H */