| Server IP : 13.213.54.232 / Your IP : 216.73.217.11 Web Server : Apache/2.4.52 (Ubuntu) System : Linux ip-172-31-17-110 6.8.0-1029-aws #31~22.04.1-Ubuntu SMP Thu Apr 24 21:16:18 UTC 2025 x86_64 User : www-data ( 33) PHP Version : 7.1.33-67+ubuntu22.04.1+deb.sury.org+1 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals, MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /lib/modules/6.8.0-1029-aws/build/arch/arc/include/asm/ |
Upload File : |
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H
#ifdef CONFIG_ISA_ARCV2
/*
* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
* due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
*
* Explicit barrier provided by DMB instruction
* - Operand supports fine grained load/store/load+store semantics
* - Ensures that selected memory operation issued before it will complete
* before any subsequent memory operation of same type
* - DMB guarantees SMP as well as local barrier semantics
* (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
* UP: barrier(), SMP: smp_*mb == *mb)
* - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
* in the general case. Plus it only provides full barrier.
*/
#define mb() asm volatile("dmb 3\n" : : : "memory")
#define rmb() asm volatile("dmb 1\n" : : : "memory")
#define wmb() asm volatile("dmb 2\n" : : : "memory")
#else
/*
* ARCompact based cores (ARC700) only have SYNC instruction which is super
* heavy weight as it flushes the pipeline as well.
* There are no real SMP implementations of such cores.
*/
#define mb() asm volatile("sync\n" : : : "memory")
#endif
#include <asm-generic/barrier.h>
#endif